Triple-Speed Ethernet Intel® FPGA IP User Guide

Download
ID 683402
Date 5/30/2022
Public
Document Table of Contents

6.1.11.2. IEEE 1588v2 TX Timestamp Signals

Table 99.  IEEE 1588v2 TX Timestamp Interface Signals
Signal I/O Width Description
tx_egress_timestamp_96b_data_n O 96 A transmit interface signal. This signal carries requested timestamp of transmitted frame with fingerprint tx_egress_timestamp_96b_fingerprint.

Consists of 48-bit seconds field, 32-bit nanoseconds field, and 16-bit fractional nanoseconds field.

tx_egress_timestamp_96b_valid O 1 A transmit interface signal. When asserted, this signal indicates that a timestamp is obtained and a timestamp request is valid for the particular frame.

Assert this signal in the same clock cycle as the start of packet (avalon_st_tx_startofpacket is asserted).

tx_egress_timestamp_96b_fingerprint O n Configurable width fingerprint that returns with correlated timestamps.

The signal width is determined by the TSTAMP_FP_WIDTH parameter (default parameter value is 4).

tx_egress_timestamp_64b_data O 64 A transmit interface signal. This signal requested timestamp of transmitted frame with fingerprint tx_egress_timestamp_64b_fingerprint.

Consists of 48-bit nanoseconds field and 16-bit fractional nanoseconds field.

tx_egress_timestamp_64b_valid O 1 A transmit interface signal. When asserted, this signal indicates that a timestamp is obtained and a timestamp request is valid for the particular frame.

Assert this signal in the same clock cycle as the start of packet (avalon_st_tx_startofpacket or avalon_st_tx_startofpacket_n is asserted).

tx_egress_timestamp_64b_fingerprint O n Configurable width fingerprint that returns with correlated timestamps.

The signal width is determined by the TSTAMP_FP_WIDTH parameter (default parameter value is 4).

Did you find the information on this page useful?

Characters remaining:

Feedback Message