Triple-Speed Ethernet Intel® FPGA IP User Guide

ID 683402
Date 5/30/2022
Public
Document Table of Contents

5.1.4. Supplementary Address (Dword Offset 0xC0 – 0xC7)

A software reset has no impact on these registers. MAC supplementary addresses are not available in 10/100 and 1000 Small MAC variations.
Table 42.  Supplementary Address Registers
Dword

Offset

Name R/W Description HW Reset
0xC0 smac_0_0 RW You can specify up to four 6-byte supplementary addresses:
  • smac_0_0/1
  • smac_1_0/1
  • smac_2_0/1
  • smac_3_0/1

Map the supplementary addresses to the respective registers in the same manner as the primary MAC address. Refer to the description of mac_0 and mac_1.

The MAC function uses the supplementary addresses for the following operations:

If you do not require the use of supplementary addresses, configure them to the primary address.

0
0xC1 smac_0_1
0xC2 smac_1_0
0xC3 smac_1_1
0xC4 smac_2_0
0xC5 smac_2_1
0xC6 smac_3_0
0xC7 smac_3_1

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