Triple-Speed Ethernet Intel® FPGA IP User Guide

ID 683402
Date 5/30/2022
Public
Document Table of Contents

6.1.10.2. Transceiver Native PHY Signal

Table 93.  Transceiver Native PHY Signal
Name I/O Description
cdr_ref_clk_n I Port to connect the RX PLL reference clock with a frequency of 125 MHz when you enable SyncE support.

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