Triple-Speed Ethernet Intel® FPGA IP User Guide

ID 683402
Date 5/30/2022
Public
Document Table of Contents

6.1.5.1. F-Tile Transceiver Direct PHY Signals

Table 82.  F-Tile Transceiver Direct PHY Signals
Name I/O Description
rx_serial_data I Positive signal for the receiver serial data.
rx_serial_data_n I Negative signal for the receiver serial data.
rx_is_lockedtodata O When asserted, this signal indicates that the CDR PLL is locked to the incoming rx_serial data.
tx_serial_data O Positive signal for the transmitter serial data.
tx_serial_data_n O Negative signal for the transmitter serial data.
tx_ready O Status signal from F-tile Native PHY. It is asserted when Native PHY TX datapath resets sequencing is complete.
rx_ready O Status signal from F-tile Native PHY. It is asserted when Native PHY RX datapath resets sequencing is complete.
FGT Transceiver Type Signals
tx_pll_refclk_link I 156.25 MHz reference clock input to F-tile Direct PHY.
rx_cdr_refclk_link I 156.25 MHz reference clock for CDR PLL.
phyip_reset_tx_in I TX reset input for TX transceivers and TX datapath of F-tile.
phyip_reset_rx_in I RX reset input for RX transceivers and RX datapath of F-tile.
phyip_reset_tx_ack_o O TX fully in reset indicator.
phyip_reset_rx_ack_o O RX fully in reset indicator.
Note: For Intel® Agilex™ F-tile devices, the reconfig_avmm interface signals are present when the reconfiguration feature is enabled.

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