Triple-Speed Ethernet Intel® FPGA IP User Guide

ID 683402
Date 5/30/2022
Public
Document Table of Contents

6.1.13.1. Clock Enablers

Table 113.  Clock Enablers
Note: The clock enabler signals are present only in SGMII mode.
Name I/O Description
rx_clkena O Receive clock enabler for SGMII 10M/100M operating speeds.
tx_clkena O Transmit clock enabler for SGMII 10M/100M operating speeds.

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