Triple-Speed Ethernet Intel® FPGA IP User Guide

ID 683402
Date 5/30/2022
Public
Document Table of Contents

2.2. Generated Files

The type of files generated in your project directory and their names may vary depending on the custom variation of the IP you created.

Table 16.  Generated Files
File Name Description
<variation_name>.v or

<variation_name>.vhd

An IP variation file, which defines a VHDL or Verilog HDL top-level description of the custom IP. Instantiate the entity defined by this file inside your design. Include this file when compiling your design in the Intel® Quartus® Prime software.
<variation_name>.bsf Intel® Quartus® Prime symbol file for the IP variation. You can use this file in the Intel® Quartus® Prime block diagram editor.
<variation_name>.qip and

<variation_name>.sip

Contains Intel® Quartus® Prime project information for your IP variations.
<variation_name>.cmp A VHDL component declaration file for the IP variation. Add the contents of this file to any VHDL architecture that instantiates the IP.
<variation_name>.spd Simulation Package Descriptor file. Specifies the files required for simulation.
Testbench Files (in <variation_name>_testbench folder)
README.txt Read me file for the testbench design.
generate_sim.qpf and

generate_sim.qsf

Dummy Intel® Quartus® Prime project and project setting file. Use this to start the Intel® Quartus® Prime in the correct directory to launch the generate_sim_verilog.tcl and generate_sim_vhdl.tcl files.
generate_sim_verilog.tcl and

generate_sim_vhdl.tcl

A Tcl script to generate the DUT VHDL or Verilog HDL simulation model for use in the testbench.
/testbench_vhdl/<variation_name>/
<variation_name>_tb.vhd or

/testbench_verilog/<variation_name>/<variation_name>_tb.v

VHDL or Verilog HDL testbench that exercises your IP variation in a third party simulator.
/testbench_vhdl/<variation_name>/run_
<variation_name>_tb.tcl or

/testbench_verilog/<variation_name>/run_
<variation_name>_tb.tcl

A Tcl script for use with the ModelSim* simulation software.
/testbench_vhdl/<variation_name>/
<variation_name>_wave.do or

/testbench_verilog/<variation_name>/
<variation_name>_wave.do

A signal tracing macro script used with the ModelSim* simulation software to display testbench signals.
/testbench_vhdl/models or

/testbench_verilog/models

A directory containing VHDL and Verilog HDL models of the Ethernet generators and monitors used by the generated testbench.

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