Triple-Speed Ethernet Intel® FPGA IP User Guide

ID 683402
Date 5/30/2022
Public
Document Table of Contents

6.1.12.1. PCS Control Interface Signals

Table 106.   Register Interface Signals
Name Avalon Memory-Mapped Signal Type I/O Description
reg_clk clk I Register access reference clock. Set the signal to a value less than or equal to 125-MHz.
reset_reg_clk reset I Active-high reset signal for reg_clk clock domain.
reg_wr write I Register write enable.
reg_rd read I Register read enable.
reg_addr[4:0] address I 16-bit word-aligned register address.
reg_data_in[15:0] writedata I Register write data. Bit 0 is the least significant bit.
reg_data_out[15:0] readdata O Register read data. Bit 0 is the least significant bit.
reg_busy waitrequest O Register interface busy. Asserted during register read or register write. A value of 0 indicates that the read or write is complete.

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