Triple-Speed Ethernet Intel® FPGA IP User Guide

ID 683402
Date 11/25/2022

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

4.1.12. PHY Management (MDIO)

This module implements the standard MDIO specification, IEEE 803.2 standard Clause 22, to access the PHY device management registers, and supports up to 32 PHY devices.

To access each PHY device, write the PHY address to the MDIO register (mdio_addr0/1) followed by the transaction data (MDIO Space 0/1). For faster access, the MAC function allows up to two PHY devices to be mapped in its register space at any one time. Subsequent transactions to the same PHYs do not require writing the PHY addresses to the register space thus reducing the transaction overhead. You can access the MDIO registers via the Avalon® memory-mapped interface.

For more information about the registers of a PHY device, refer to the specification provided with the device.

For more information about the MDIO registers, refer to the MAC Configuration Register Space section.