Triple-Speed Ethernet Intel® FPGA IP User Guide

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ID 683402
Date 5/30/2022
Public
Document Table of Contents

6.1.12.4. GMII

Table 109.  GMII Signals
Name I/O Description
GMII Transmit Interface
gmii_tx_d[7:0] I GMII transmit data bus.
gmii_tx_en I Assert this signal to indicate that the data on gmii_tx_d[7:0]is valid.
gmii_tx_err I Assert this signal to indicate to the PHY device that the current frame sent is invalid.
GMII Receive Interface
gmii_rx_d[7:0] O GMII receive data bus.
gmii_rx_dv O Asserted to indicate that the data on gmii_rx_d[7:0] is valid. Stays asserted during frame reception, from the first preamble byte until the last byte in the CRC field is received.
gmii_rx_err O Asserted by the PHY to indicate that the current frame contains errors.

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