Triple-Speed Ethernet Intel® FPGA IP User Guide

ID 683402
Date 5/30/2022
Public
Document Table of Contents

6.1.13.3. TBI Interface Signals

If the core variation does not include an embedded PMA, the PCS block provides a 62.5-MHz 2 ten-bit interface (TBI) to an external SERDES chip.
Table 115.  TBI Interface Signals for External SERDES Chip
Name I/O Description 17
tbi2x_tx_d[19:0] O 2X TBI transmit data. The PCS function transmits data on this bus synchronous to tbi2x_tx_clk.
tbi2x_tx_clk I 62.5-MHz TBI transmit clock from external SERDES, typically sourced by the local reference clock oscillator.
Note: If connected to the E-tile Native PHY and F-tile Transceiver PHY, this signal can be sourced from tx_clkout.
tbi2x_rx_clk I 62.5-MHz TBI receive clock from external SERDES, typically sourced by the clock recovered from the encoded serial data.
Note: If connected to the E-tile Native PHY and F-tile Transceiver PHY, this signal can be sourced from rx_clkout.
tbi2x_rx_d[19:0] I 2X TBI receive data. This bus carries the data from the external SERDES. Synchronize the bus with tbi2x_rx_clk.
17 All the signals in this table are not exported to the top level for 10/100/1000Mb Ethernet MAC with 1000BASE-X/SGMII 2XTBI PCS with E-tile GXB variant.

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