Triple-Speed Ethernet Intel® FPGA IP User Guide

ID 683402
Date 11/25/2022

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

4.1.6. FIFO Buffer Thresholds

For MAC variations with internal FIFO buffers, you can change the operations of the FIFO buffers, and manage potential FIFO buffer overflow or underflow by configuring the following thresholds:
  • Almost empty
  • Almost full
  • Section empty
  • Section full

These thresholds are defined in bytes for 8-bit wide FIFO buffers and in words for 32-bit wide FIFO buffers. The FIFO buffer thresholds are configured via the registers.