Triple-Speed Ethernet Intel® FPGA IP User Guide

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ID 683402
Date 5/30/2022
Public
Document Table of Contents

6.1.1.1. Clock and Reset Signals

Data transfers on the MAC Ethernet-side interface are synchronous to the receive and transmit clocks.
Table 55.  GMII/RGMII/MII Clock Signals
Name I/O Description
tx_clk

(In Platform Designer: pcs_mac_tx_clock_connection)

I GMII/RGMII/MII transmit clock. Provides the timing reference for all GMII / MII transmit signals. The values of gm_tx_d[7:0], gm_tx_en, gm_tx_err, and of m_tx_d[3:0], m_tx_en, m_tx_err are valid on the rising edge of tx_clk.
rx_clk

(In Platform Designer: pcs_mac_rx_clock_connection)

I GMII/RGMII/MII receive clock. Provides the timing reference for all rx related signals. The values of gm_rx_d[7:0], gm_rx_dv, gm_rx_err, and of m_rx_d[3:0], m_rx_en, m_rx_err are valid on the rising edge of rx_clk.
Table 56.   Reset Signal
Name I/O Description
reset I Assert this signal to reset all logic in the MAC and PCS control interface. The signal must be asserted for at least three clock cycles.

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