3.2. Ethernet MAC Options
- Enable MAC 10/100 half duplex support (10/100 Small MAC variations)
- Align packet headers to 32-bit boundary (10/100 and 1000 Small MAC variations)
|Ethernet MAC Options|
|Enable MAC 10/100 half duplex support||On/Off||Turn on this option to include support for half duplex operation on 10/100 Mbps connections.|
|Enable local loopback on MII/GMII/RGMII||On/Off||Turn on this option to enable local loopback on the MAC’s MII, GMII, or RGMII interface. If you turn on this option, the loopback function can be dynamically enabled or disabled during system operation via the MAC configuration register.|
|Enable supplemental MAC unicast addresses||On/Off||Turn on this option to include support for supplementary destination MAC unicast addresses for fast hardware-based received frame filtering.|
|Include statistics counters||On/Off||Turn on this option to include support for simple network monitoring protocol (SNMP) management information base (MIB) and remote monitoring (RMON) statistics counter registers for incoming and outgoing Ethernet packets.
By default, the width of all statistics counters are 32 bits.
|Enable 64-bit statistics byte counters||On/Off||Turn on this option to extend the width of selected statistics counters— aOctetsTransmittedOK, aOctetsReceivedOK, and etherStatsOctets—to 64 bits.|
|Include multicast hashtable||On/Off||Turn on this option to implement a hash table, a fast hardware-based mechanism to detect and filter multicast destination MAC address in received Ethernet packets.|
|Align packet headers to 32-bit boundary||On/Off||Turn on this option to include logic that aligns all packet headers to a 32-bit boundary. This helps reduce software overhead processing in realignment of data buffers.
This option is available for MAC variations with 32 bits wide internal FIFO buffers and MAC variations without internal FIFO buffers.
You must turn on this option if you intend to use the Triple-Speed Ethernet Intel® FPGA IP with the Interniche TCP/IP protocol stack.
|Enable full-duplex flow control||On/Off||Turn on this option to include the logic for full-duplex flow control that includes pause frames generation and termination.|
|Enable VLAN detection||On/Off||Turn on this option to include the logic for VLAN and stacked VLAN frame detection. When turned off, the MAC does not detect VLAN and staked VLAN frames. The MAC forwards these frames to the user application without processing them.|
|Enable magic packet detection||On/Off||Turn on this option to include logic for magic packet detection (Wake-on LAN).|
|Include MDIO module (MDC/MDIO)||On/Off||Turn on this option if you want to access external PHY devices connected to the MAC function. When turned off, the core does not include the logic or signals associated with the MDIO interface.|
|Host clock divisor||—||Clock divisor to divide the MAC control interface clock to produce the MDC clock output on the MDIO interface. The default value is 40.
For example, if the MAC control interface clock frequency is 100 MHz and the desired MDC clock frequency is 2.5 MHz, a host clock divisor of 40 should be specified.
Intel recommends that the division factor is defined such that the MDC frequency does not exceed 2.5 MHz.