Triple-Speed Ethernet Intel® FPGA IP User Guide

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ID 683402
Date 5/30/2022
Public
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9.6.3. Simulation Model Files

Previously, the Triple-Speed Ethernet Intel® FPGA IP generates a <variation_name>.vho or <variation_name>.vo file for VHDL or Verilog HDL IP functional simulation model.

For the new Triple-Speed Ethernet Intel® FPGA IP created in Intel® Quartus® Prime software version 13.0, the simulation model will be generated using the industrial standard IEEE simulation encryption.

The following table lists the scripts available for you to compile the simulation model files in a standalone flow.

Note: The simulation support is different in Intel® Quartus® Prime Windows and Linux version. Therefore, some of the files generated can be used only in the Linux environment. Refer to the Intel® Quartus® Prime User Guide: Third-party Simulation for more details.
Table 123.  Simulation Model Files
Directory Name Description
sim/mentor/ Contains a ModelSim* script msim_setup.tcl to set up and run a simulation.
Note: The ModelSim* -AE simulator is not supported for 10/100/1000 Ethernet MAC with 1000BASE-X/SGMII 2XTBI PCS variant. You must use another supported ModelSim* simulator such as ModelSim* SE.
sim/synopsys/vcs/ Contains a shell script vcs_setup.sh to set up and run a VCS* simulation.
sim/synopsys/vcsmx/ Contains a shell script vcsmx_setup.sh and synopsys_sim.setup to set up and run a VCS* MX simulation.
sim/aldec/ Contains a Riviera-PRO* script rivierapro_setup.tcl to set up and run a simulation.
Note: Riviera simulator is not supported for 10/100/1000 Ethernet MAC with 1000BASE-X/SGMII 2XTBI PCS variant.
sim/xcelium/ Contains a shell script xcelium_setup.tcl and other setup files to set up and run a simulation.

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