Triple-Speed Ethernet Intel® FPGA IP User Guide

ID 683402
Date 11/25/2022

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6.2.4. GMII Receive

On receive, all signals are sampled on the rising edge of rx_clk. The GMII data enable signal gm_rx_dv is asserted by the PHY to indicate the start of a new frame and remains asserted until the last byte of the frame is present on the gm_rx_d[7:0] bus. Between frames, gm_rx_dv remains deasserted.

If the PHY detects an error on the frame received from the line, the PHY asserts the GMII error signal, gm_rx_err, for at least one clock cycle at any time during the frame transfer.

A frame received on the GMII interface with a PHY error indication is subsequently transferred on the Avalon® streaming interface with the error signal rx_err[0] asserted.