Triple-Speed Ethernet Intel® FPGA IP User Guide

ID 683402
Date 11/25/2022

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

7.3. Sharing PLLs in Devices with GIGE PHY

For Cyclone® V designs that contain multiple instances of MAC and PCS with PMA or PCS with PMA variation targeting devices with GIGE PHY, you can share the PLLs by placing the associated signals (tx_p, rx_p, and ref_clk) to the same I/O block of transceiver bank through pin assignment. Additionally, the rx_recovclkout clock must be buffered by two levels of inverter in the top level module so that it can be fitted to the general I/O pins.

Did you find the information on this page useful?

Characters remaining:

Feedback Message