Triple-Speed Ethernet Intel® FPGA IP User Guide

ID 683402
Date 11/25/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

6.1.2.3. Multiport MAC Transmit Interface Signals

Table 70.  MAC Transmit Interface Signals
Name Avalon Streaming Signal Type I/O Description
Avalon Streaming Signals
data_tx_valid_n valid I Transmit data valid. Assert this signal to indicate that the data on the following signals are valid: data_tx_data_n, data_tx_sop_n, data_tx_eop_n, and data_tx_error_n.
data_tx_data_n[7:0] data I Transmit data.
data_tx_sop_n startofpacket I Transmit start of packet. Assert this signal when the first byte in the frame is driven on data_tx_data_n.
data_tx_eop_n endofpacket I Transmit end of packet. Assert this signal when the last byte in the frame (the last byte of the FCS field) is driven on data_tx_data_n.
data_tx_error_n[4:0] error I Transmit frame error. Assert this signal with the final byte in the frame to indicate that the transmit frame is invalid. The MAC function then forwards the frame to the GMII with error.
data_tx_ready_n ready O MAC ready. When asserted, this signal indicates that the MAC function is ready to accept data from the user application.
Component-Specific Signal
tx_crc_fwd_n I Transmit CRC insertion. Assert this active-low signal when data_tx_eop_n is asserted for the MAC function to compute the CRC and insert it into the frame. Otherwise, the user application is expected to provide the CRC.