Triple-Speed Ethernet Intel® FPGA IP User Guide

ID 683402
Date 5/30/2022
Public
Document Table of Contents

6.1.12.5. MII

Table 110.  MII Signals
Name I/O Description
MII Transmit Interface
mii_tx_d[3:0] I MII transmit data bus.
mii_tx_en I Assert this signal to indicate that the data on mii_tx_d[3:0]is valid.
mii_tx_err I Assert this signal to indicate to the PHY device that the frame sent is invalid.
MII Receive Interface
mii_rx_d[3:0] O MII receive data bus.
mii_rx_dv O Asserted to indicate that the data on mii_rx_d[3:0]is valid. The signal stays asserted during frame reception, from the first preamble byte until the last byte of the CRC field is received.
mii_rx_err O Asserted by the PHY to indicate that the current frame contains errors.
mii_col O Collision detection. Asserted by the PCS function to indicate that a collision was detected during frame transmission.
mii_crs O Carrier sense detection. Asserted by the PCS function to indicate that a transmit or receive activity is detected on the Ethernet line.

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