Triple-Speed Ethernet Intel® FPGA IP User Guide

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ID 683402
Date 5/30/2022
Public
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9.5. Test Flow

The testbench performs the following operations upon a simulated power-on reset:
  • Initializes the DUT registers.
  • Starts transmission. For a single-channel MAC with internal FIFO buffers, clears the FIFOs.
  • Ends transmission and checks the following elements to determine that the simulation is successful:
    • No Ethernet protocol errors detected.
    • Ethernet frames generated and transmitted are received by the frame monitor.

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