Triple-Speed Ethernet Intel® FPGA IP User Guide

ID 683402
Date 5/30/2022
Document Table of Contents MDIO Frame Format

The MDIO master communicates with the slave PHY device using MDIO frames. A complete frame is 64 bits long and consists of 32-bit preamble, 14-bit command, 2-bit bus direction change, and 16-bit data. Each bit is transferred on the rising edge of the MDIO clock, mdc.
Table 31.  MDIO Frame Formats (Read/Write)Field settings for MDIO transactions.
Type PRE Command

MSB      LSB







TA Data

MSB                 LSB

Read 1 ... 1 01 10 xxxxx xxxxx Z0 xxxxxxxxxxxxxxxx Z
Write 1 ... 1 01 01 xxxxx xxxxx 10 xxxxxxxxxxxxxxxx Z
Table 32.  MDIO Frame Field Descriptions
Name Description
PRE Preamble. 32 bits of logical 1 sent prior to every transaction.
ST Start indication. Standard MDIO (Clause 22): 0b01.
OP Opcode. Defines the transaction type.
Addr1 The PHY device address (PHYAD). Up to 32 devices can be addressed. For PHY device 0, the Addr1 field is set to the value configured in the mdio_addr0 register. For PHY device 1, the Addr1 field is set to the value configured in the mdio_addr1 register.
Addr2 Register Address. Each PHY can have up to 32 registers.
TA Turnaround time. Two bit times are reserved for read operations to switch the data bus from write to read for read operations. The PHY device presents its register contents in the data phase and drives the bus from the 2nd bit of the turnaround phase.
Data 16-bit data written to or read from the PHY device.
Idle Between frames, the MDIO data signal is tri-stated.

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