Triple-Speed Ethernet Intel® FPGA IP User Guide

ID 683402
Date 5/30/2022
Public
Document Table of Contents

4.1.2. MAC Interfaces

The MAC function implements the following interfaces:
  • Avalon® streaming interface on the system side.
    • Avalon® streaming sink port on transmit with the following properties:
      • Fixed data width, 8 bits, in MAC variations without internal FIFO buffers; configurable data width, 8 or 32 bits, in MAC variations with internal FIFO buffers.
      • Packet support using start-of-packet (SOP) and end-of-packet (EOP) signals, and partial final packet signals.
      • Error reporting.
      • Variable-length ready latency specified by the tx_almost_full register.
    • Avalon® streaming source port on receive with the following properties:
      • Fixed data width of 8 bits in MAC variations without internal FIFO buffers; configurable data width, 8 or 32 bits, in MAC variations with internal FIFO buffers.
      • Backpressure is supported only in MAC variations with internal FIFO buffers. Transmission stops when the level of the FIFO buffer reaches the respective programmable thresholds.
      • Packet support using SOP and EOP signals, and partial final packet signals.
      • Error reporting.
      • Ready latency is zero in MAC variations without internal FIFO buffers. In MAC variations with internal FIFO buffers, the ready latency is two.
  • Media independent interfaces on the network side—select MII, GMII, or RGMII by setting the Interface option on the Core Configuration page or the ETH_SPEED bit in the command_config register.
  • Control interface—an Avalon® memory-mapped slave port that provides access to 256 32-bit configuration and status registers, and statistics counters. This interface supports the use of waitrequest to stall the interconnect fabric for as many cycles as required.
  • PHY management interface—implements the standard MDIO specification, IEEE 803.2 standard Clause 22, to access the PHY device management registers. This interface supports up to 32 PHY devices.

MAC variations without internal FIFO buffers implement the following additional interfaces:

  • FIFO status interface—an Avalon® streaming sink port that streams in the fill level of an external FIFO buffer. Only MAC variations without internal buffers implement this interface.
  • Packet classification interface—an Avalon® streaming source port that streams out receive packet classification information. Only MAC variations without internal buffers implement this interface.

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