Triple-Speed Ethernet Intel® FPGA IP User Guide

ID 683402
Date 5/30/2022
Public
Document Table of Contents

5.2.2. Status Register (Word Offset 0x01)

Table 49.  Status Register Bit Descriptions
Bit Name R/W Description
0 EXTENDED_CAPABILITY RO A value of 1 indicates that the PCS function supports extended registers.
1 JABBER_DETECT Unused. Always set to 0.
2 LINK_STATUS RO A value of 1 indicates that a valid link is established. A value of 0 indicates an invalid link.

If the link synchronization is lost, a 0 is latched.

3 AUTO_NEGOTIATION_ABILITY RO A value of 1 indicates that the PCS function supports auto-negotiation.
4 REMOTE_FAULT Unused. Always set to 0.
5 AUTO_NEGOTIATION_COMPLETE RO A value of 1 indicates the following status:
  • The auto-negotiation process is completed.
  • The auto-negotiation control registers are valid.
6 MF_PREAMBLE_SUPPRESSION Unused. Always set to 0.
7 UNIDIRECTIONAL_ABILITY RO A value of 1 indicates that the PCS is able to transmit from MII/GMII regardless of whether the PCS has established a valid link.
8 EXTENDED_STATUS Unused. Always set to 0.
9 100BASET2_HALF_DUPLEX RO The PCS function does not support 100Base-T2, 10-Mbps, 100BASE-X, and 100Base-T4 operation. Always set to 0.
10 100BASET2_FULL_DUPLEX
11 10MBPS_HALF_DUPLEX
12 10MBPS_FULL_DUPLEX
13 100BASE-X_HALF_DUPLEX
14 100BASE-X_FULL_DUPLEX
15 100BASE-T4

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