Triple-Speed Ethernet Intel® FPGA IP User Guide

ID 683402
Date 11/25/2022

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6.1.9. 10/100/1000 Multiport Ethernet MAC with 1000BASE-X/SGMII PCS Signals

Figure 56. 10/100/1000 Multiport Ethernet MAC Function without Internal FIFO Buffers with 1000BASE-X/SGMII PCS Signals

Table 91.  References
Interface Signal Section
Clock and reset signals Clock and Reset Signals
MAC control interface signals MAC Control Interface Signals
MAC transmit interface signals MAC Transmit Interface Signals
MAC receive interface signals MAC Receive Interface Signals
MAC packet classification signals Multiport MAC Packet Classification Signals
MAC FIFO status signals Multiport MAC FIFO Status Signals
Pause and magic packet signals Pause and Magic Packet Signals
PHY management signals PHY Management Signals
Ten-bit interface signals TBI Interface Signals
Status LED signals Status LED Control Signals
SERDES control signals SERDES Control Signals