Triple-Speed Ethernet Intel® FPGA IP User Guide

ID 683402
Date 5/30/2022
Public
Document Table of Contents

6.1.1.6. MAC Transmit Interface Signals

Table 63.  MAC Transmit Interface Signals
Name Avalon Streaming Signal Type I/O Description
Avalon Streaming Signals
ff_tx_clk

(In Platform Designer: transmit_clock_connection)

clk I Transmit clock. All transmit signals are synchronized on the rising edge of this clock.

Set this clock to the required frequency to get the desired bandwidth on the Avalon streaming transmit interface. This clock can be completely independent from tx_clk.

ff_tx_wren valid I Transmit data write enable. Assert this signal to indicate that the data on the following signals are valid: ff_tx_data[(DATAWIDTH-1):0], ff_tx_sop, and ff_tx_eop.

In cut-through mode, keep this signal asserted throughout the frame transmission. Otherwise, the frame is truncated and forwarded to the Ethernet-side interface with an error.

ff_tx_data[(DATAWIDTH-1):0] data I Transmit data. DATAWIDTH can be either 8 or 32 depending on the FIFO data width configured. When DATAWIDTH is 32, the first byte transmitted is ff_tx_data[31:24] followed by ff_tx_data[23:16] and so forth.
ff_tx_mod[1:0] empty I Transmit data modulo. Indicates invalid bytes in the final frame word:
  • 11: ff_tx_data[23:0] is not valid
  • 10: ff_tx_data[15:0] is not valid
  • 01: ff_tx_data[7:0] is not valid
  • 00: ff_tx_data[31:0] is valid

This signal applies only when DATAWIDTH is set to 32.

ff_tx_sop startofpacket I Transmit start of packet. Assert this signal when the first byte in the frame (the first byte of the destination address) is driven on ff_tx_data.
ff_tx_eop endofpacket I Transmit end of packet. Assert this signal when the last byte in the frame (the last byte of the FCS field) is driven on ff_tx_data.
ff_tx_err error I Transmit frame error. Assert this signal with the final byte in the frame to indicate that the transmit frame is invalid. The MAC function forwards the invalid frame to the GMII with an error.
ff_tx_rdy ready O MAC ready. When asserted, the MAC function is ready to accept data from the user application.
Component-Specific Signals
ff_tx_crc_fwd I Transmit CRC insertion. Set this signal to 0 when ff_tx_eop is set to 1 to instruct the MAC function to compute a CRC and insert it into the frame. If this signal is set to 1, the user application is expected to provide the CRC.
tx_ff_uflow O Asserted when an underflow occurs on the transmit FIFO buffer.
ff_tx_septy O Deasserted when the FIFO buffer is filled to or above the section-empty threshold defined in the tx_section_empty register. User applications can use this signal to indicate when to stop writing to the FIFO buffer and initiate backpressure.
ff_tx_a_full O Asserted when the transmit FIFO buffer reaches the almost- full threshold.
ff_tx_a_empty O Asserted when the transmit FIFO buffer goes below the almost-empty threshold.

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