Triple-Speed Ethernet Intel® FPGA IP User Guide

ID 683402
Date 5/30/2022
Public
Document Table of Contents

6.1.4. 10/100/1000 Ethernet MAC with 1000BASE-X/SGMII 2XTBI PCS and Embedded PMA Signals (E-Tile)

Figure 51. 10/100/1000 Ethernet MAC Function with Internal FIFO Buffers, and 1000BASE-X/SGMII 2XTBI PCS Signals With Embedded PMA Signals (E-Tile)

Note to 10/100/1000 Ethernet MAC Function with Internal FIFO Buffers, and 1000BASE-X/SGMII 2XTBI PCS Signals With Embedded PMA Signals:

  1. The DATAWIDTH value depends on the FIFO width that you select in the parameter editor. Options available are 8 and 32 bits.
Table 78.  References
Interface Signal Section
Reset signals Reset Signals
MAC control interface signals MAC Control Interface Signals
Pause and magic packet signals Pause and Magic Packet Signals
Status LED control signals Status LED Control Signals
MAC transmit interface signals MAC Transmit Interface Signals
MAC receive interface signals MAC Receive Interface Signals
PHY management PHY Management Signals
IEEE 1588v2 Time-of-Day (TOD) clock IEEE 1588v2 Time-of-Day (TOD) Clock Interface Signals
IEEE 1588v2 PCS phase management clock IEEE 1588v2 PCS Phase Measurement Clock Signal
IEEE 1588v2 TX insert control timestamp interface signals IEEE 1588v2 TX Insert Control Timestamp Signals
IEEE 1588v2 TX timestamp request signals IEEE 1588v2 TX Timestamp Request Signals
IEEE 1588v2 TX timestamp interface signals IEEE 1588v2 TX Timestamp Signals
IEEE 1588v2 RX timestamp interface signals IEEE 1588v2 RX Timestamp Signals

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