Triple-Speed Ethernet Intel® FPGA IP User Guide

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ID 683402
Date 5/30/2022
Public
Document Table of Contents

6.1.11.1. IEEE 1588v2 RX Timestamp Signals

Table 98.  IEEE 1588v2 RX Timestamp Interface Signals
Signal I/O Width Description
rx_ingress_timestamp_96b_data_n O 96 Carries the ingress timestamp on the receive datapath. Consists of 48-bit seconds field, 32-bit nanoseconds field, and 16-bit fractional nanoseconds field.

The MAC presents the timestamp for all receive frames and asserts this signal in the same clock cycle it asserts rx_ingress_timestamp_96b_valid.

rx_ingress_timestamp_96b_valid O 1 When asserted, this signal indicates that rx_ingress_timestamp_96b_data contains valid timestamp.

For all receive frame, the MAC asserts this signal in the same clock cycle it receives the start of packet (avalon_st_rx_startofpacket is asserted).

rx_ingress_timestamp_64b_data O 64 Carries the ingress timestamp on the receive datapath. Consists of 48-bit nanoseconds field and 16-bit fractional nanoseconds field.

The MAC presents the timestamp for all receive frames and asserts this signal in the same clock cycle it asserts rx_ingress_timestamp_64b_valid.

rx_ingress_timestamp_64b_valid O 1 When asserted, this signal indicates that rx_ingress_timestamp_64b_data contains valid timestamp.

For all receive frame, the MAC asserts this signal in the same clock cycle it receives the start of packet (avalon_st_rx_startofpacket is asserted).

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