Triple-Speed Ethernet Intel® FPGA IP User Guide

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ID 683402
Date 5/30/2022
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6.1.4.2. E-Tile Transceiver Native PHY Signals

Table 80.  E-Tile Transceiver Native PHY Signals
Name I/O Description
pll_refclk0 I Reference clock for the E-tile Native PHY transceiver. Set this clock to 156.25 MHz.
rx_serial_data I Positive signal for the receiver serial data.
rx_serial_data_n I Negative signal for the receiver serial data.
rx_is_lockedtodata O When asserted, this signal indicates that the CDR PLL is locked to the incoming rx_serial data.
tx_serial_data O Positive signal for the transmitter serial data.
tx_serial_data_n O Negative signal for the transmitter serial data.
rx_ready O Status signal from E-tile Native PHY. It is asserted when Native PHY RX datapath resets sequencing is complete.
tx_ready O Status signal from E-tile Native PHY. It is asserted when Native PHY TX datapath resets sequencing is complete.
Note: For Intel® Stratix® 10 E-tile and Intel® Agilex™ devices, the reconfig_avmm interface signals are present when the reconfiguration feature is enabled. Refer to the E-Tile Transceiver PHY User Guide for more information on the interface signals.

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