Triple-Speed Ethernet Intel® FPGA IP User Guide

ID 683402
Date 5/30/2022
Public
Document Table of Contents

6.2.6. RGMII Receive

On receive all signals are sampled on both edges of rx_clk. The RGMII control signal rx_control is asserted by the PHY to indicate the start of a new frame and remains asserted until the last upper nibble of the frame is present on rgmii_in[3:0] bus. Between frames, rx_control remains deasserted.
Figure 72. RGMII Receive in 10/100 Mbps


Figure 73. RGMII Receive in 1000 Mbps


A frame received on the RGMII interface with a PHY error indication is subsequently transferred on the Avalon® streaming interface with the error signal rx_err[0] asserted.

Figure 74. RGMII Receive with Error in Gigabit Mode


The current implementation of the RGMII receive interface expects a positive-delay rx_clk relative to the receive data (the clock comes after the data).

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