Triple-Speed Ethernet Intel® FPGA IP User Guide

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ID 683402
Date 5/30/2022
Public
Document Table of Contents

5.2.3.2. SGMII MAC Mode Auto Negotiation

When the SGMII mode and the SGMII MAC mode auto-negotiation are enabled, the Triple-Speed Ethernet Intel® FPGA IP ignores the value in the dev_ability register and automatically sets the value to 16’h4001 as specified in the SGMII specification for SGMII auto-negotiation.

When the auto-negotiation is complete, the Triple-Speed Ethernet Intel® FPGA IP speed and the duplex mode will be resolved based on the value in the partner_ability register. The partner_ability register is received from the link partner during the auto-negotiation process.

Table 51.  Partner_Ability Register Bits Description in SGMII MAC Mode
Bit(s) Name R/W Description
9:0 Reserved
11:10 COPPER_SPEED[1:0] RO Link partner interface speed:
  • 00: Copper interface speed is 10 Mbps.
  • 01: Copper interface speed is 100 Mbps.
  • 10: Copper interface speed is 1 gigabit.
  • 11: Reserved.
12 COPPER_DUPLEX_STATUS RO Link partner duplex capability:
  • 1: Copper interface is capable of operating in full-duplex mode.
  • 0: Copper interface is capable of operating in half-duplex mode.
13 Reserved
14 ACK RO Acknowledge. A value of 1 indicates that the link partner has received 3 consecutive matching ability values from the device.
15 COPPER_LINK_STATUS RO Copper link partner status:
  • 1: Copper interface link is up.
  • 0: Copper interface link is down.

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