Triple-Speed Ethernet Intel® FPGA IP User Guide

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ID 683402
Date 5/30/2022
Public
Document Table of Contents

5.3. Register Initialization

The Triple-Speed Ethernet Intel® FPGA IP supports various types of interface commonly used by the following Ethernet solutions:
  • MII/GMII
  • RGMII
  • 10-bit Interface
  • SGMII
  • 1000BASE-X
  • Management Data Input/Output (MDIO) for external PHY register configuration

When using the Triple-Speed Ethernet Intel® FPGA IP with an external interface, you must understand the requirements and initialize the registers.

Register initialization mainly performed in the following configurations:

  • External PHY Initialization using MDIO (Optional)
  • PCS Configuration Register Initialization
  • MAC Configuration Register Initialization

This section discusses the register initialization for the following examples of the Ethernet system using different MAC interfaces with recommended initialization sequences:

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