Visible to Intel only — GUID: bhc1410931994231
Ixiasoft
Visible to Intel only — GUID: bhc1410931994231
Ixiasoft
5.3. Register Initialization
- MII/GMII
- RGMII
- 10-bit Interface
- SGMII
- 1000BASE-X
- Management Data Input/Output (MDIO) for external PHY register configuration
When using the Triple-Speed Ethernet Intel® FPGA IP with an external interface, you must understand the requirements and initialize the registers.
Register initialization mainly performed in the following configurations:
- External PHY Initialization using MDIO (Optional)
- PCS Configuration Register Initialization
- MAC Configuration Register Initialization
This section discusses the register initialization for the following examples of the Ethernet system using different MAC interfaces with recommended initialization sequences:
Did you find the information on this page useful?
Feedback Message
Characters remaining: