Triple-Speed Ethernet Intel® FPGA IP User Guide

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ID 683402
Date 5/30/2022
Public
Document Table of Contents

6.2.9. IEEE 1588v2 Timestamp

The following timing diagrams show the timestamp of frames observed on TX path for the IEEE 1588v2 feature.

Figure below shows the TX timestamp signals for the IEEE 1588v2 feature in a 1-step operation.

In a 1-step operation, a TX egress timestamp is inserted into timestamp field of the PTP frame in the MAC. You need to drive the 1-step related signal appropriately so that the timestamp can be inserted into the correct location of the packet. The input signals related to the 2-step operation are not important and can be driven low or ignored.

Figure 75. Egress Timestamp Insert for IEEE 1588v2 PTP Packet Encapsulated in IEEE 802.3


Type 1 Egress Correction Field Update shows the TX timestamp signals for the first type of egress correction field update, where the residence time is calculated by subtracting 96 bit ingress timestamp from 96 bit egress timestamp. The result is updated in the correction field of the PTP frame encapsulated over UDP/IPv4.

The tx_etstamp_ins_ctrl_residence_time_calc_format signal is driven low to indicate that this is a 96b residence time calculation. The tx_etstamp_ins_ctrl_checksum_zero signal is driven high to clear the UDP/IPv4 checksum field to all 0.

Figure 76. Type 1 Egress Correction Field Update


Type 2 Egress Correction Field Update shows the TX timestamp signals for the second type of egress correction field update, where the 64 bit ingress timestamp has been pre-subtracted from the correction field at the ingress port. At the egress port, the 64  bit egress timestamp is added into the correction field and the correct residence time is updated in the correction field. This is the example of PTP frame encapsulated over UPD/IPV6.

The tx_etstamp_ins_ctrl_residence_time_calc_format signal is driven high to indicate that this is a 64b residence time calculation. The tx_etstamp_ins_ctrl_checksum_correct signal is driven high to correct the packet UPD/IPV6 checksum by updating the checksum correction field.

Figure 77. Type 2 Egress Correction Field Update


Egress 2-Step Operation shows the TX timestamp signals for the IEEE 1588v2 feature in a two step operation.

When the tx_egress_timestamp_request_valid signal is driven high with a unique fingerprint, the MAC returns an egress timestamp associated with that unique fingerprint. The signals related to the 1-step operation can be driven low or ignored. There is no modification to the packet content.

Figure 78. Egress 2-Step Operation


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