Triple-Speed Ethernet Intel® FPGA IP User Guide

ID 683402
Date 5/30/2022
Public
Document Table of Contents

7.4. Sharing Transceiver Quads

For designs that contain multiple PMA blocks targeting Intel FPGA device families with GX transceivers, you can combine the transceiver channels in the same quad. To share the same transceiver quad, the transceiver channels must have the same dynamic reconfiguration setting. In other words, you must turn on dynamic reconfiguration capabilities in all channels in a quad even though you only intend to use these capabilities in some of the channels.

The dynamic reconfiguration is always turned on in devices other than Arria® GX and Stratix® II GX. When the dynamic reconfiguration is turned on in designs targeting devices other than Intel® Arria® 10, Stratix® V, Arria® V, Intel® Cyclone® 10 GX, and Cyclone® V, Intel recommends that you connect the dynamic reconfiguration signals to the ALTGX_RECONFIG megafunction.

In Stratix® V, Arria® V, and Cyclone® V devices, Intel recommends that you connect the dynamic reconfiguration signals to the Transceiver Reconfiguration Controller megafunction. For transceiver quad sharing between Triple-Speed Ethernet Intel® FPGA IP and other IPs that target these devices, reset signal for all the cores must be from the same source.

Refer to the respective device handbook for more information on dynamic reconfiguration signals in Intel FPGA devices.

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