Triple-Speed Ethernet Intel® FPGA IP User Guide

ID 683402
Date 5/30/2022
Public
Document Table of Contents

5.1.6. Deterministic Latency (Dword Offset 0xE1– 0xE3)

Table 44.  Deterministic Latency Configuration and Status Register
Dword Offset Name Bit R/W Description HW Reset
0xE1 dl_reset [1] RW

Deterministic latency (DL) soft reset.

Provides a soft reset to the deterministic latency block.
  • 0: DL block is not under reset
  • 1: DL block is being reset
Note: This is not a self-clearing reset.
0x0
measure_valid [0] RO Indicates whether the DL measurement values are valid.
  • 0: Not valid
  • 1: Valid
0x0
0xE2 tx_delay [20:0] RO

TX datapath latency.

Displays the TX datapath DL measurement values measured in the i_dl_sampling_clk cycles.

measure_valid must be set prior taking the measurement.

0x0
0xE3 rx_delay [20:0] RO

RX datapath latency

Displays the RX datapath DL measurement values measured in the i_dl_sampling_clk cycles.

measure_valid must be set prior taking the measurement.

0x0

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