Triple-Speed Ethernet Intel® FPGA IP User Guide

ID 683402
Date 5/30/2022
Public
Document Table of Contents

6.1.8. 10/100/1000 Ethernet MAC Without Internal FIFO Buffers with IEEE 1588v2, 1000BASE-X/SGMII 2XTBI PCS, SGMII Bridge, and Deterministic Latency Signals

Figure 55. 10/100/1000 Ethernet MAC Function Without Internal FIFO Buffers with IEEE 1588v2, 1000BASE-X/SGMII 2XTBI PCS, SGMII Bridge, and Determistic Latency Signals
Table 85.  References
Interface Signal Section
Clock and reset signals Reset Signals
MAC receive interface signals Multiport MAC Receive Interface Signals
MAC transmit interface signals Multiport MAC Transmit Interface Signals
MAC packet classification signals Multiport MAC Packet Classification Signals
MAC FIFO status signals Multiport MAC FIFO Status Signals
Magic packet signals Pause and Magic Packet Signals
Status LED signals Status LED Control Signals
MAC control interface signals MAC Control Interface Signals
Ten-bit interface signals TBI Interface Signals
IEEE 1588v2 RX timestamp signals IEEE 1588v2 RX Timestamp Signals
IEEE 1588v2 TX timestamp signals IEEE 1588v2 TX Timestamp Signals
IEEE 1588v2 TX timestamp request signals IEEE 1588v2 TX Timestamp Request Signals
IEEE 1588v2 TX insert control timestamp signals IEEE 1588v2 TX Insert Control Timestamp Signals
IEEE 1588v2 TOD clock interface signals IEEE 1588v2 Time-of-Day (TOD) Clock Interface Signals
IEEE 1588v2 PCS phase measurement clock signal IEEE 1588v2 PCS Phase Measurement Clock Signal

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