Triple-Speed Ethernet Intel® FPGA IP User Guide

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ID 683402
Date 5/30/2022
Public
Document Table of Contents

1.2. Device Family Support

The IP provides the following support for Intel® FPGA device families.

Table 2.   Intel FPGA IP Device Support Levels
Device Support Level Definition
Advance The IP is available for simulation and compilation for this device family. Timing models include initial engineering estimates of delays based on early post-layout information. The timing models are subject to change as silicon testing improves the correlation between the actual silicon and the timing models. You can use this IP for system architecture and resource utilization studies, simulation, pinout, system latency assessments, basic timing assessments (pipeline budgeting), and I/O transfer strategy (datapath width, burst depth, I/O standards tradeoffs).
Preliminary The IP is verified with preliminary timing models for this device family. The IP meets all functional requirements, but might still be undergoing timing analysis for the device family. It can be used in production designs with caution.
Final The IP is verified with final timing models for this device family. The IP meets all functional and timing requirements for the device family and can be used in production designs.
Table 3.  Device Family Support for Triple-Speed Ethernet MAC
Device Family Support Minimum Speed Grade

with 1588 Feature

Intel® Agilex™ (E-tile and F-tile) Preliminary Not supported
Intel® Stratix® 10 (E-tile) Final -I3
Intel® Stratix® 10 (L-tile and H-tile) Final -I3
Stratix® V Final -I3
Stratix® IV Final Not supported
Intel® Arria® 10 Final -I3
Arria® V Final -I5
Arria® II Final Not supported
Intel® Cyclone® 10 GX Final -I5
Intel® Cyclone® 10 LP Final Not supported
Cyclone® V Final -I7
Cyclone® IV Final Not supported
Intel® MAX® 10 Final -I7

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