Triple-Speed Ethernet Intel® FPGA IP User Guide

ID 683402
Date 5/30/2022
Public
Document Table of Contents

6.1.8.3. Deterministic Latency Control and Status Interface Signals

Table 88.  Deterministic Latency Control and Status Interface Signals
Name I/O Width Description
i_sl_rx_hard_fifo_pempty I 1 PMA RX FIFO partial empty status signal. This signal asserts when the fill level reaches the number of unwritten entries in the FIFO buffer before the buffer is empty.
o_sl_hard_fifo_rd_en O 1 Read enable signal to the PMA. When asserted, this signal indicates that the data can be read from the RX PMA interface.
i_tx_pma_ready I 1 Ready status signal of the transmitter PMA.
i_rx_pma_ready I 1 Ready status signal of the receiver PMA.
i_tx_ready I 1 Ready status signal of the TX transceiver channel.
i_rx_ready I 1 Ready status signal of the RX transceiver channel.

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