Triple-Speed Ethernet Intel® FPGA IP User Guide

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ID 683402
Date 5/30/2022
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6.1.12.6. SGMII Status Signals

The SGMII status signals provide status information to the PCS block. When the PCS is instantiated standalone, these signals are inputs to the MAC and serve as interface control signals for that block.
Table 111.  SGMII Status Signals
Name I/O Description
set_1000 O Gigabit mode enabled. In 1000BASE-X, this signal is always set to 1. In SGMII, this signal is set to 1 if one of the following conditions is met:
  • The USE_SGMII_AN bit is set to 1 and a gigabit link is established with the link partner, as decoded from the partner_ability register.
  • The USE_SGMII_AN bit is set to 0 and the SGMII_SPEED bit is set to 10.
set_100 O 100 -Mbps mode enabled. In 1000BASE-X, this signal is always set to 0. In SGMII, this signal is set to 1 if one of the following conditions is met:
  • The USE_SGMII_AN bit is set to 1 and a 100Mbps link is established with the link partner, as decoded from the partner_ability register.
  • The USE_SGMII_AN bit is set to 0 and the SGMII_SPEED bit is set to 01.
set_10 O 10 -Mbps mode enabled. In 1000BASE-X, this signal is always set to 0. In SGMII, this signal is set to 1 if one of the following conditions is met:
  • The USE_SGMII_AN bit is set to 1 and a 10Mbps link is established with the link partner, as decoded from the partner_ability register.
  • The USE_SGMII_AN bit is set to 0 and the SGMII_SPEED bit is set to 00.
hd_ena O Half-duplex mode enabled. In 1000BASE-X, this signal is always set to 0. In SGMII, this signal is set to 1 if one of the following conditions is met:
  • The USE_SGMII_AN bit is set to 1 and a half-duplex link is established with the link partner, as decoded from the partner_ability register.
  • The USE_SGMII_AN bit is set to 0 and the SGMII_DUPLEX bit is set to 1.

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