Triple-Speed Ethernet Intel® FPGA IP User Guide

ID 683402
Date 5/30/2022
Public
Document Table of Contents

6.1.12.2. PCS Reset Signals

Table 107.   Reset Signals
Name I/O Description
reset_rx_clk I Active-high reset signal for PCS rx_clk clock domain. Assert this signal to reset the logic synchronized by rx_clk.
reset_tx_clk I Active-high reset signal for PCS tx_clk clock domain. Assert this signal to reset the logic synchronized by tx_clk.

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