Triple-Speed Ethernet Intel® FPGA IP User Guide

ID 683402
Date 5/30/2022
Public
Document Table of Contents

6.1.1.3. MAC Control Interface Signals

The MAC control interface is an Avalon memory-mapped slave port that provides access to the register space.
Table 58.  MAC Control Interface Signals
Name Avalon Memory-Mapped Signal Type I/O Description
clk clk I Register access reference clock. Set the signal to a value less than or equal to 125 MHz.
reg_wr write I Register write enable.
reg_rd read I Register read enable.
reg_addr[7:0] address I 32-bit word-aligned register address.
reg_data_in[31:0] writedata I Register write data. Bit 0 is the least significant bit.
reg_data_out[31:0] readdata O Register read data. Bit 0 is the least significant bit.
reg_busy waitrequest O Register interface busy. Asserted during register read or register write access; deasserted when the current register access completes.

This signal can be high or low during idle cycles and reset. Therefore, the user application must not make any assumption of its assertion state during these periods.

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