Intel provides timing constraint files (.sdc) to ensure that the Triple-Speed Ethernet Intel® FPGA IP meets the design timing requirements in Intel FPGA devices. The files constraints the false paths and multi-cycle paths in the Triple-Speed Ethernet Intel® FPGA IP. The timing constraints files are specified in the <variation_name>.qip file and is automatically included in the Intel® Quartus® Prime project files.
You may need to add timing constraints that are external to the IP. The following sections describe the procedure to create the timing constraint file.