Triple-Speed Ethernet Intel® FPGA IP User Guide

ID 683402
Date 5/30/2022
Public
Document Table of Contents

10.1. Driver Architecture

Figure 87.  Triple-Speed Ethernet Software Driver Architecture


Notes to Triple-Speed Ethernet Software Driver Architecture:

  1. The first n bytes are reserved for SGDMA descriptors, where n = (Total number of descriptors + 3) × 32. Applications must not use this memory region.
  2. For MAC variations without internal FIFO buffers, the transmit and receive FIFOs are external to the MAC function.

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