Triple-Speed Ethernet Intel® FPGA IP User Guide

ID 683402
Date 5/30/2022
Public
Document Table of Contents

2.1.2. Generating a Design Example or Simulation Model

After you have parameterized the IP, you can also generate a design example, in addition to generating the IP component files.

Note: Generating a design example can increase processing time.

In the parameter editor, click Example Design: "testbench" to create a functional simulation model (design example that includes a testbench). The testbench and the automated script are located in the <variation name>_testbench directory.

Note: Generate Example Design: "testbench" option only generates the design for functional simulation.

You can now integrate your custom IP instance in your design, simulate, and compile. While integrating your IP instance into your design, you must make appropriate pin assignments. You can create a virtual pin to avoid making specific pin assignments for top-level signals while you are simulating and not ready to map the design to hardware.

In the parameter editor, click Example Design: "example_design" to create the design example for the hardware test and simulation model for specific IP configurations on Intel® Stratix® 10 E-tile devices. Please refer to the Triple-Speed Ethernet Intel® Stratix® 10 FPGA IP Design Example User Guide for more details.

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