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Visible to Intel only — GUID: bhc1410931510089
Ixiasoft
Visible to Intel only — GUID: bhc1410931510089
Ixiasoft
5.1.3. Transmit and Receive Command Registers (Dword Offset 0x3A – 0x3B)
The following table describes the registers that determine how the MAC function processes transmit and receive frames. A software reset does not change the values in these registers.
Dword Offset |
Name | R/W | Description |
---|---|---|---|
0x3A | tx_cmd_stat | RW | Specifies how the MAC function processes transmit frames. When you turn on the Align packet headers to 32-bit boundaries option, this register resets to 0x00040000 upon a hardware reset. Otherwise, it resets to 0x00.
|
0x3B | rx_cmd_stat | RW | Specifies how the MAC function processes receive frames. When you turn on the Align packet headers to 32-bit boundaries option, this register resets to 0x02000000 upon a hardware reset. Otherwise, it resets to 0x00.
|