Triple-Speed Ethernet Intel® FPGA IP User Guide

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ID 683402
Date 5/30/2022
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7.6. Clocking Scheme of MAC with 2XTBI PCS and Embedded PMA

The following is the clocking scheme of the design that contains MAC with 2XTBI and embedded PMA on E-tile and F-tile:
  • 2XTBI PCS runs on 125 MHz and 62.5 MHz clocks while the same 125 MHz clock is used by MAC.
  • The 125 MHz and 62.5 MHz clocks must be synchronous, in which their rising edges must align and must have 0 ppm and phase shift.
  • The E-tile Native PHY and F-tile Direct PHY are the embedded PMAs in this variant. The tx_clkout and rx_clkout on the E-tile Native PHY and F-tile Direct PHY are used as clock sources for 2XTBI PCS tbi2x_tx_clk and tbi2x_rx_clk.
  • Logic is implemented in the PCS block for clock rate matching by default regardless whether the ENABLE_SGMII option is selected. Therefore, the 125 MHz and 62.5 MHz clocks do not need to be at 0 ppm in comparison with tx_clkout and rx_clkout, which are usually provided by external SERDES.
  • The E-tile Native PHY and F-tile Direct PHY transceivers are driven by the 156.25 MHz clock.
  • The reference clock input to the F-tile Direct PHY, tx_pll_refclk_link and rx_cdr_refclk_link, should be driven by the 156.25 MHz system PLL output.
Table 120.  Clock Signals Visible at Top-Level DesignClock signals that are visible at the top-level design for each possible configuration.
Clocks Configurations 22
MAC and 2XTBI PCS with PMA 2XTBI PCS Only
clk Yes N/A
reg_clk No Yes
ff_tx_clk Yes N/A
ff_rx_clk Yes N/A
tx_clk_125 Yes Yes
rx_clk_125 Yes Yes
tx_clk_62_5 Yes Yes
rx_clk_62_5 Yes Yes
tbi2x_tx_clk No Yes
tbi2x_rx_clk No Yes
pll_refclk0 23 Yes N/A
tx_clkout 23 No N/A
rx_clkout 23 No N/A
tx_pll_refclk_link 24 Yes N/A
rx_cdr_refclk_link 24 Yes N/A
Figure 83. Clock Connectivity in MAC with 2XTBI PCS and Embedded PMA (E-Tile)
Figure 84. Clock Connectivity in MAC with 2XTBI PCS and Embedded PMA (F-Tile)

Notes to Clock Connectivity in MAC with 2XTBI PCS and Embedded PMA (E-Tile) and Clock Connectivity in MAC with 2XTBI PCS and Embedded PMA (F-Tile):

  1. Intel® recommends that the rx_clk_125, tx_clk_125, rx_clk_62_5, and tx_clk_62_5 share the same clock source.
  2. Therefore, Intel® recommends you to use one IOPLL with two output clocks to get the 125 MHz and 62.5 MHz clocks and connect to both the TX and RX datapaths.
  3. rx_clkout and tx_clkout are output clocks generated by the E-tile transceiver Native PHY and F-tile transceiver Direct PHY and internally connected to tbi2x_rx_clk and tbi2x_tx_clk in the variant MAC with 2XTBI and embedded PMA.
  4. The reg_clk clock is internally connected to clk in the variant MAC with 2XTBI and embedded PMA. Refer to Register Interface Signals for more information about reg_clk.
  5. Intel recommends 156.25 MHz frequency for this clock source when the F-tile Reference and System PLL Clocks is used to drive the Triple-Speed Ethernet IP only.
22 Yes indicates that the clock is visible at the top-level design.

No indicates that the clock is not visible at the top-level design.

N/A indicates that the clock is not applicable for the given configuration.

23 Clock signals of E-tile transceiver Native PHY.
24 Clock signals of F-tile transceiver Direct PHY.

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