22.214.171.124. SGMII PHY Mode Auto Negotiation
When the auto-negotiation is complete, Triple-Speed Ethernet Intel® FPGA IP speed and the duplex mode will be resolved based on the value that you set in the dev_ability register. You can get the value for the dev_ability register from the system level where the Triple-Speed Ethernet Intel® FPGA IP is integrated. If the IP is integrated in the system level with another IP that resolves the copper speed and duplex information, use these values to set the dev_ability register.
|9:0||Reserved||—||Always set bit 0 to 1 and bits 1–9 to 0.|
|11:10||SPEED[1:0]||RW||Link partner interface speed:
|12||COPPER_DUPLEX_STATUS||RW||Link partner duplex capability:
|13||Reserved||—||Always set this bit to 0.|
|14||ACK||RO||Acknowledge. Value as specified in the IEEE 802.3z standard.|
|15||COPPER_LINK_STATUS||RW||Copper link partner status: