Triple-Speed Ethernet Intel® FPGA IP User Guide

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ID 683402
Date 5/30/2022
Public
Document Table of Contents

5.2.3.3. SGMII PHY Mode Auto Negotiation

When the SGMII mode and the SGMII PHY mode auto-negotiation is enabled, set the dev_ability register before the auto-negotiation process so that the link partner can identify the copper speed, duplex status, and link status.

When the auto-negotiation is complete, Triple-Speed Ethernet Intel® FPGA IP speed and the duplex mode will be resolved based on the value that you set in the dev_ability register. You can get the value for the dev_ability register from the system level where the Triple-Speed Ethernet Intel® FPGA IP is integrated. If the IP is integrated in the system level with another IP that resolves the copper speed and duplex information, use these values to set the dev_ability register.

Table 52.  Dev_Ability Register Bits Description in SGMII PHY Mode
Bit(s) Name R/W Description
9:0 Reserved Always set bit 0 to 1 and bits 1–9 to 0.
11:10 SPEED[1:0] RW Link partner interface speed:
  • 00: Copper interface speed is 10 Mbps.
  • 01: Copper interface speed is 100 Mbps.
  • 10: Copper interface speed is 1 gigabit.
  • 11: Reserved.
12 COPPER_DUPLEX_STATUS RW Link partner duplex capability:
  • 1: Copper interface is capable of operating in full-duplex mode
  • 0: Copper interface is capable of operating in half-duplex mode
  • 1 Gbps speed does not support half-duplex mode.
13 Reserved Always set this bit to 0.
14 ACK RO Acknowledge. Value as specified in the IEEE 802.3z standard.
15 COPPER_LINK_STATUS RW Copper link partner status:
  • 1: Copper interface link is up.
  • 0: Copper interface link is down.

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