A newer version of this document is available. Customers should click here to go to the newest version.
Visible to Intel only — GUID: bhc1410932236649
Ixiasoft
Visible to Intel only — GUID: bhc1410932236649
Ixiasoft
10.7. Constants
The following lists all constants defined for the MAC registers manipulation and provides links to detailed descriptions of the registers. It also list the constants that define the MAC operating mode and timeout values.
Constant | Value | Description |
---|---|---|
ALTERA_TSE_DUPLEX_MODE_DEFAULT | 1 | 0: Half-duplex 1:Full-duplex |
ALTERA_TSE_MAC_SPEED_DEFAULT | 0 | 0: 10 Mbps 1: 100 Mbps 2: 1000 Mbps |
ALTERA_TSE_SGDMA_RX_DESC_CHAIN_SIZE | 1 | The number of SG-DMA descriptors required for the current operating mode. |
ALTERA_CHECKLINK_TIMEOUT_THRESHOLD | 1000000 | The timeout value when the MAC tries to establish a link with a PHY. |
ALTERA_AUTONEG_TIMEOUT_THRESHOLD | 250000 | The auto-negotiation timeout value. |
Command_Config Register (Command_Config Register (Dword Offset 0x02)) | ||
ALTERA_TSEMAC_CMD_TX_ENA_OFST | 0 | Configures the TX_ENA bit. |
ALTERA_TSEMAC_CMD_TX_ENA_MSK | 0x1 | |
ALTERA_TSEMAC_CMD_RX_ENA_OFST | 1 | Configures the RX_ENA bit. |
ALTERA_TSEMAC_CMD_RX_ENA_MSK | 0x2 | |
ALTERA_TSEMAC_CMD_XON_GEN_OFST | 2 | Configures the XON_GEN bit. |
ALTERA_TSEMAC_CMD_XON_GEN_MSK | 0x4 | |
ALTERA_TSEMAC_CMD_ETH_SPEED_OFST | 3 | Configures the ETH_SPEED bit. |
ALTERA_TSEMAC_CMD_ETH_SPEED_MSK | 0x8 | |
ALTERA_TSEMAC_CMD_PROMIS_EN_OFST | 4 | Configures the PROMIS_EN bit. |
ALTERA_TSEMAC_CMD_PROMIS_EN_MSK | 0x10 | |
ALTERA_TSEMAC_CMD_PAD_EN_OFST | 5 | Configures the PAD_EN bit. |
ALTERA_TSEMAC_CMD_PAD_EN_MSK | 0x20 | |
ALTERA_TSEMAC_CMD_CRC_FWD_OFST | 6 | Configures the CRC_FWD bit. |
ALTERA_TSEMAC_CMD_CRC_FWD_MSK | 0x40 | |
ALTERA_TSEMAC_CMD_PAUSE_FWD_OFST | 7 | Configures the PAUSE_FWD bit. |
ALTERA_TSEMAC_CMD_PAUSE_FWD_MSK | 0x80 | |
ALTERA_TSEMAC_CMD_PAUSE_IGNORE_OFST | 8 | Configures the PAUSE_IGNORE bit. |
ALTERA_TSEMAC_CMD_PAUSE_IGNORE_MSK | 0x100 | |
ALTERA_TSEMAC_CMD_TX_ADDR_INS_OFST | 9 | Configures the TX_ADDR_INS bit. |
ALTERA_TSEMAC_CMD_TX_ADDR_INS_MSK | 0x200 | |
ALTERA_TSEMAC_CMD_HD_ENA_OFST | 10 | Configures the HD_ENA bit. |
ALTERA_TSEMAC_CMD_HD_ENA_MSK | 0x400 | |
ALTERA_TSEMAC_CMD_EXCESS_COL_OFST | 11 | Configures the EXCESS_COL bit. |
ALTERA_TSEMAC_CMD_EXCESS_COL_MSK | 0x800 | |
ALTERA_TSEMAC_CMD_LATE_COL_OFST | 12 | Configures the LATE_COL bit. |
ALTERA_TSEMAC_CMD_LATE_COL_MSK | 0x1000 | |
ALTERA_TSEMAC_CMD_SW_RESET_OFST | 13 | Configures the SW_RESET bit. |
ALTERA_TSEMAC_CMD_SW_RESET_MSK | 0x2000 | |
ALTERA_TSEMAC_CMD_MHASH_SEL_OFST | 14 | Configures the MHASH_SEL bit. |
ALTERA_TSEMAC_CMD_MHASH_SEL_MSK | 0x4000 | |
ALTERA_TSEMAC_CMD_LOOPBACK_OFST | 15 | Configures the LOOP_ENA bit. |
ALTERA_TSEMAC_CMD_LOOPBACK_MSK | 0x8000 | |
ALTERA_TSEMAC_CMD_TX_ADDR_SEL_OFST | 16 | Configures the TX_ADDR_SEL bits (bits 16 - 18). |
ALTERA_TSEMAC_CMD_TX_ADDR_SEL_MSK | 0x70000 | |
ALTERA_TSEMAC_CMD_MAGIC_ENA_OFST | 19 | Configures the MAGIC_ENA bit. |
ALTERA_TSEMAC_CMD_MAGIC_ENA_MSK | 0x80000 | |
ALTERA_TSEMAC_CMD_SLEEP_OFST | 20 | Configures the SLEEP bit. |
ALTERA_TSEMAC_CMD_SLEEP_MSK | 0x100000 | |
ALTERA_TSEMAC_CMD_WAKEUP_OFST | 21 | Configures the WAKEUP bit. |
ALTERA_TSEMAC_CMD_WAKEUP_MSK | 0x200000 | |
ALTERA_TSEMAC_CMD_XOFF_GEN_OFST | 22 | Configures the XOFF_GEN bit. |
ALTERA_TSEMAC_CMD_XOFF_GEN_MSK | 0x400000 | |
ALTERA_TSEMAC_CMD_CNTL_FRM_ENA_OFST | 23 | Configures the CNTL_FRM_ENA bit. |
ALTERA_TSEMAC_CMD_CNTL_FRM_ENA_MSK | 0x800000 | |
ALTERA_TSEMAC_CMD_NO_LENGTH_CHECK_OFST | 24 | Configures the NO_LENGTH_CHECK bit. |
ALTERA_TSEMAC_CMD_NO_LENGTH_CHECK_MSK | 0x1000000 | |
ALTERA_TSEMAC_CMD_ENA_10_OFST | 25 | Configures the ENA_10 bit. |
ALTERA_TSEMAC_CMD_ENA_10_MSK | 0x2000000 | |
ALTERA_TSEMAC_CMD_RX_ERR_DISC_OFST | 26 | Configures the RX_ERR_DISC bit. |
ALTERA_TSEMAC_CMD_RX_ERR_DISC_MSK | 0x4000000 | |
ALTERA_TSEMAC_CMD_CNT_RESET_OFST | 31 | Configures the CNT_RESET bit. |
ALTERA_TSEMAC_CMD_CNT_RESET_MSK | 0x80000000 | |
Tx_Cmd_Stat Register (Transmit and Receive Command Registers (Dword Offset 0x3A – 0x3B)) | ||
ALTERA_TSEMAC_TX_CMD_STAT_OMITCRC_OFST | 17 | Configures the OMIT_CRC bit. |
ALTERA_TSEMAC_TX_CMD_STAT_OMITCRC_MSK | 0x20000 | |
ALTERA_TSEMAC_TX_CMD_STAT_TXSHIFT16_OFST | 18 | Configures the TX_SHIFT16 bit. |
ALTERA_TSEMAC_TX_CMD_STAT_TXSHIFT16_MSK | 0x40000 | |
Rx_Cmd_Stat Register (Transmit and Receive Command Registers (Dword Offset 0x3A – 0x3B)) | ||
ALTERA_TSEMAC_RX_CMD_STAT_RXSHIFT16_OFST | 25 | Configures the RX_SHIFT16 bit |
ALTERA_TSEMAC_RX_CMD_STAT_RXSHIFT16_MSK | 0x2000000 |