Triple-Speed Ethernet Intel® FPGA IP User Guide

ID 683402
Date 5/30/2022
Public
Document Table of Contents

9.6.1. Generate the Simulation Model

The generated design example includes both Verilog HDL and VHDL testbench files for the device under test (DUT)—your custom IP variation.

To generate a Verilog functional simulation model, use the command prompt and run the quartus_sh -t generate_sim_verilog.tcl file. Alternatively, perform the following steps:

  1. Launch the Intel® Quartus® Prime software and browse to the <variation name>_testbench directory.
  2. Open the generate_sim.qpf file from the project directory.
  3. On the Tools menu, select Tcl Scripts and select the generate_sim_verilog.tcl file.
  4. Click Run.

To generate a VHDL functional simulation model, you can use the command prompt and run the quartus_sh -t generate_sim_vhdl.tcl file. Alternatively, perform the following steps:

  1. Launch the Intel® Quartus® Prime software and browse to the <variation name>_testbench directory.
  2. Open the generate_sim.qpf file from the project directory.
  3. On the Tools menu, select Tcl Scripts and browse to the generate_sim_vhdl.tcl file.
  4. Click Run.

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