Triple-Speed Ethernet Intel® FPGA IP User Guide

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ID 683402
Date 5/30/2022
Public
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6.1.11.4. IEEE 1588v2 TX Insert Control Timestamp Signals

Table 101.  IEEE 1588v2 TX Insert Control Timestamp Interface Signals
Signal I/O Width Description
tx_etstamp_ins_ctrl_timestamp_insert_n I 1 Assert this signal to insert egress timestamp into the associated frame.

Assert this signal in the same clock cycle as the start of packet (avalon_st_tx_startofpacket is asserted).

tx_etstamp_ins_ctrl_timestamp_format I 1 Timestamp format of the frame, which the timestamp inserts.

0: 1588v2 format (48-bits second field + 32-bits nanosecond field + 16-bits correction field for fractional nanosecond)

Required offset location of timestamp and correction field.

1: 1588v1 format (32-bits second field + 32-bits nanosecond field)

Required offset location of timestamp.

Assert this signal in the same clock cycle as the start of packet (avalon_st_tx_startofpacket is asserted).

tx_etstamp_ins_ctrl_residence_time_update I 1 Assert this signal to add residence time (egress timestamp –ingress timestamp) into correction field of PTP frame.

Required offset location of correction field (tx_etstamp_ins_ctrl_offset_correction_field).

Assert this signal in the same clock cycle as the start of packet (avalon_st_tx_startofpacket is asserted).

tx_etstamp_ins_ctrl_ingress_timestamp_96b[] I 96 96-bit format of ingress timestamp.

(48 bits second + 32 bits nanosecond + 16 bits fractional nanosecond).

Assert this signal in the same clock cycle as the start of packet (avalon_st_tx_startofpacket is asserted).

tx_etstamp_ins_ ctrl_ingress_timestamp_64b[] I 64 64-bit format of ingress timestamp.

(48-bits nanosecond + 16-bits fractional nanosecond).

Assert this signal in the same clock cycle as the start of packet (avalon_st_tx_startofpacket is asserted).

tx_etstamp_ins_ctrl_residence_time_calc_format I 1 Format of timestamp to be used for residence time calculation.

0: 96-bits (96-bits egress timestamp - 96-bits ingress timestamp).

1: 64-bits (64-bits egress timestamp - 64-bits ingress timestamp).

Assert this signal in the same clock cycle as the start of packet (avalon_st_tx_startofpacket is asserted).

tx_etstamp_ins_ctrl_checksum_zero I 1 Assert this signal to set the checksum field of UDP/IPv4 to zero.

Required offset location of checksum field (tx_etstamp_ins_ctrl_offset_checksum_field).

Assert this signal in the same clock cycle as the start of packet (avalon_st_tx_startofpacket is asserted).

tx_etstamp_ins_ctrl_checksum_correct I 1 Assert this signal to correct UDP/IPv6 packet checksum, by updating the checksum correction, which is specified by checksum correction offset.

Required offset location of checksum correction (tx_etstamp_ins_ctrl_offset_checksum_correction).

Assert this signal in the same clock cycle as the start of packet (avalon_st_tx_startofpacket is asserted).

tx_etstamp_ins_ctrl_offset_timestamp I 1 The location of the timestamp field, relative to the first byte of the packet.

Assert this signal in the same clock cycle as the start of packet (avalon_st_tx_startofpacket is asserted).

tx_etstamp_ins_ctrl_offset_correction_field[] I 16 The location of the correction field, relative to the first byte of the packet.

Assert this signal in the same clock cycle as the start of packet (avalon_st_tx_startofpacket is asserted).

tx_etstamp_ins_ctrl_offset_checksum_field[] I 16 The location of the checksum field, relative to the first byte of the packet.

Assert this signal in the same clock cycle as the start of packet (avalon_st_tx_startofpacket is asserted).

tx_etstamp_ins_ctrl_offset_checksum_correction[] I 16 The location of the checksum correction field, relative to the first byte of the packet.

Assert this signal in the same clock cycle as the start of packet (avalon_st_tx_startofpacket is asserted).

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