Triple-Speed Ethernet Intel® FPGA IP User Guide

ID 683402
Date 5/30/2022
Public
Document Table of Contents

7.1. Optimizing Clock Resources in Multiport MAC with PCS and Embedded PMA

The following factors determine the total number of global and regional clock resources required by your system:
  • Configuration of the Triple-Speed Ethernet Intel® FPGA IP and the blocks it contains
  • PCS operating mode (SGMII or 1000BASE-X)
  • PMA technology implemented in the target device
  • Number of clocks that can share a single source
  • Number of PMAs required in the design
  • ALTGX megafunction operating mode

You can use the same clock source to drive clocks that are visible at the top-level design, thus reducing the total number of clock sources required by the entire design.

Table 117.  Clock Signals Visible at Top-Level DesignClock signals that are visible at the top-level design for each possible configuration.
Clocks Configurations 18
MAC Only MAC and PCS MAC and PCS with PMA
rx_recovclkout Yes
ref_clk 19 19 Yes
clk Yes Yes Yes
ff_tx_clk 20 Yes Yes Yes
ff_rx_clk 20 Yes Yes Yes
tx_clk Yes No No
rx_clk Yes No No
tbi_rx_clk Yes No
tbi_tx_clk Yes No
gxb_cal_blk_clk 21 Yes
reconfig_clk Yes
18 Yes indicates that the clock is visible at the top-level design. 
No indicates that the clock is not visible at the top-level design. 
— indicates that the clock is not applicable for the given configuration.
19 This clock is visible at the top-level design and needs to be connected to a clock source for the multiport fifoless Ethernet MAC ONLY and fifoless Ethernet MAC with SGMII PCS configurations. For single channel fifoless MAC configuration ONLY and fifoless MAC with SGMII disabled in PCS, this clock is not used and can be tied to GND.
20 These signals are only visible on the single port MAC with internal FIFO buffers. They are only visible when the multiport Ethernet design is implemented through the replication of the single port MAC with internal FIFO buffers.
21 Applies to GX transceiver.

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