Triple-Speed Ethernet Intel® FPGA IP User Guide

ID 683402
Date 5/30/2022
Public
Document Table of Contents

1.3. Features

  • Complete triple-speed Ethernet IP: 10/100/1000 Mbps Ethernet MAC, 1000BASE-X/SGMII PCS, and embedded PMA.
  • Successful validation from the University of New Hampshire InterOperability Lab.
  • 10/100/1000 Mbps Ethernet MAC features:
    • Multiple variations: 10/100/1000 Mbps Ethernet MAC in full duplex, 10/100 Mbps Ethernet MAC in half duplex, 10/100 Mbps or 1000 Mbps small MAC (resource-efficient variant), and multiport MAC that supports up to 24 ports
    • Support for basic, virtual LAN (VLAN), stacked VLAN, and jumbo Ethernet frames. Also supports control frames including pause frames
    • Optional internal FIFO buffers, depth from 64 bytes to 256 Kbytes
    • Optional statistics counters
  • MAC interfaces:
    • Client side—8 bit or 32 bit Avalon® streaming interface
    • Network side—MII, GMII, or RGMII on the network side. Optional loopback on these interfaces.
    • Optional management data input/output (MDIO) master interface for PHY device management.
  • 1000BASE-X/SGMII PCS features:
    • Compliance with Clause 36 of the IEEE standard 802.3.
    • Optional embedded PMA implemented with serial transceiver or LVDS I/O and soft clock data recovery (CDR) in Intel FPGA devices that support this interface at 1.25 Gbps data rate.
    • Support for auto-negotiation as defined in Clause 37.
    • Support for connection to 1000BASE-X PHYs. Support for 10BASE-T, 100BASE-T, and 1000BASE-T PHYs if the PHYs support SGMII.
  • PCS interfaces:
    • Client side—MII or GMII
    • Network side—ten-bit interface (TBI) for PCS without PMA; 1.25 Gbps serial interface for PCS with PMA implemented with serial transceiver or LVDS I/O and soft CDR in Intel FPGA devices that support this interface at 1.25 Gbps data rate.
  • Programmable features via 32 bit configuration registers:
    • FIFO buffer thresholds.
    • Pause quanta for flow control.
    • Source and destination MAC addresses.
    • Address filtering on receive, up to 5 unicast and 64 multicast MAC addresses.
    • Promiscuous mode—receive frame filtering is disabled in this mode.
    • Frame length—in MAC only variation, up to 64 Kbytes including jumbo frames. In all variants containing 1000BASE-X/SGMII PCS (with or without MAC), the frame length is up to 10 Kbytes.
    • Optional auto-negotiation for the 1000BASE-X/SGMII PCS.
  • Error correction code protection feature for internal memory blocks.
  • Optional IEEE 1588v2 feature for 10/100/1000 Mbps Ethernet MAC with SGMII PCS and embedded serial PMA variation operating without internal FIFO buffer in full-duplex mode, 10/100/1000 Mbps MAC with SGMII PCS and embedded LVDS I/O, variation operating without internal FIFO buffer in full-duplex mode, or MAC only variation operating without internal FIFO buffer in full-duplex mode. This feature is supported in Intel® Stratix® 10, Arria® V, Intel® Arria® 10, Intel® Cyclone® 10 GX, Cyclone® V, Intel® MAX® 10, and Stratix® V device families. This feature is also supported in the Intel® Stratix® 10 E-tile transceiver variant (10/100/1000 Mbps Ethernet MAC with 1000BASE-X/SGMII 2XTBI PCS variation operating without internal FIFO buffer in full-duplex mode).
  • Optional deterministic latency feature for 10/100/1000 Mbps Ethernet MAC with 1000BASE-X/SGMII 2XTBI PCS and IEEE 1588v2 feature enabled variation operating without internal FIFO buffer in full-duplex mode. This feature is only supported in the Intel® Stratix® 10 E-tile devices.

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